A static random access memory (SRAM) array employs a collection of cross-coupled CMOS inverters as memory elements having NMOS and PMOS transistors. Typically, the NMOS transistors are used as pull-down devices, and the PMOS transistors are used as pull-up devices. The NMOS transistors are contained in a p-substrate and the PMOS transistors are contained in an n-well within the p-substrate.
It is becoming increasingly difficult to have an SRAM design that is robust for the overall conditions in which it is required to operate. Two key parameters affecting this realm are the static noise margin (SNM), which is its robustness against upset and the trip voltage (Vtrip), which provides a measure of the ability to write into the SRAM cell. The SRAM cell needs to provide a balance (i.e., maintain a level of robustness) between the two functions of reading and writing. Worst case for the SNM is high temperature while worst case for the Vtrip is low temperature. If there is a good balance between SNM and Vtrip at low temperature, there will be an imbalance at high temperature, generally.
The robustness may be measured in terms of the standard deviation SIGMA of local parameter variation within the SRAM cell. There are different parameters in a particular transistor that will vary randomly. The primary parameter is related to the doping employed to fabricate the transistor. Doping is done by an implantation process, which generates a somewhat Gaussian distribution of dopants per unit area. This causes parameter variation (primarily in the threshold voltage) from one transistor to the next on a local basis
Local variations of transistor characteristics provide variation of the SNM such that there is a distribution of the SNM for local SRAM cells from one memory SRAM cell to the next memory SRAM cell. The memory cell SNM bears a linear relationship to the threshold voltage. Therefore, a Gaussian distribution of the threshold voltage provides a Gaussian distribution of the SNMs thereby allowing the local SIGMA of a particular cell to be considered. Since there are a large number of SRAM cells on a chip and there is no control over this local variation, a design margin is needed that accommodates the variation. Therefore, having a tolerance of five SIGMA worth of variation is deemed to provide reasonable robustness.
Figure of merit (FOM) is a measure of the robustness in terms of this local variation. A FOM of five indicates that there is adequate SNM over a five SIGMA range. Table 1 provides exemplary FOMs pertaining to SNM for two positive supply voltages and over three operating temperatures of a SRAM. Similarly, Table 2 provides exemplary FOMs pertaining to Vtrip for the same positive supply voltages and over the same operating temperatures of the SRAM. As a third variable, an n-well voltage Vnwell is applied.
As may be seen in Tables 1 and 2 for any value of n-well voltage Vnwell, the FOMs for SNM decrease with increasing temperature, and the FOMs for Vtrip decrease with decreasing temperature. SNM is worst case at high temperature while Vtrip is worst case at low temperature, as noted above. Generally then, what improves SNM degrades Vtrip and vice-versa. It may also be noted that although the n-well voltages selected vary over a fairly wide margin, each value of Vnwell produces a FOM that is less than five at some temperature within the normal operating range, which is typically −40 to +125 degrees C. Therefore, the design space for adequate SNM and adequate Vtrip is reduced by the required temperature range of operation.
TABLE 1SRAM Cell SNM FOM ExampleSNM FOMs for Vnwell equal to:VDDTEMPVDD − 0.5 VVDDVDD + 0.5 V1.8 V1.0 V −40 C.7.67.36.96.71.0 V  0 C.7.26.96.56.31.0 V+125 C.5.65.24.84.61.3 V −40 C.8.28.18.08.01.3 V  0 C.7.57.47.27.21.3 V 125 C.5.65.35.05.0
TABLE 2SRAM Cell Vtrip FOM ExampleVtrip FOMs for Vnwell equal to:VDDTEMPVDD − 0.5 VVDDVDD + 0.5 V1.8 V1.0 V −40 C.4.14.44.851.0 V  0 C.4.64.95.45.61.0 V+125 C.6.16.47.17.31.3 V −40 C.7.37.78.18.11.3 V  0 C.7.88.28.88.81.3 V 125 C.9.410.010.710.7
Accordingly, what is needed in the art is a way to provide adequate SNM and Vtrip for a SRAM array over a broader operating temperature range.